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Lattice Semiconductor introduced the Lattice MachXO5-NX TDQ family, a secure control FPGAs with full Commercial National Security Algorithm (CNSA) 2.0-compliant post-quantum cryptography (PQC) support.
Built on the Lattice Nexus platform, MachXO5-NX TDQ FPGAs deliver security, reliability, and flexibility for Computing, Communications, Industrial, and Automotive applications as the threat of quantum-enabled cyberattacks rises.
“Quantum computing advances increase the urgency to adopt quantum-resistant security across every industry,” said Esam Elashmawi, Chief Strategy and Marketing officer, Lattice Semiconductor. “With MachXO5-NX TDQ, Lattice is first to market with a secure control FPGA family that not only meets today’s security mandates but also delivers crypto-agility and hardware root of trust to future-proof our customers’ infrastructure against evolving threats.”
The Lattice MachXO5-NX TDQ FPGA family equips customers with:
Full suite of CNSA 2.0 compliant PQC
- Complete CNSA 2.0 and National Institute of Standards and Technology (NIST)-approved PQC algorithms (LMS, XMSS, ML-DSA, ML-KEM, AES256-GCM, SHA2, SHA3, SHAKE) for protection against quantum threats
- Authenticated and/or encrypted bitstream ensuring data integrity and protection against unauthorized access with ML-DSA, LMS, XMSS, AES256
- Unique, patent pending crypto-agility with in-field algorithm update capability and anti-rollback version protection to enable ongoing alignment with evolving standards
- Secure bitstream key management with revokable root keys and sophisticated key hierarchy for both PQC and classical keys
Advanced cryptography
- Full complement of advanced symmetric and classical asymmetric cryptographic algorithms (AES-CBC/GCM 256 bit, ECDSA-384/521, SHA-384/512, RSA 3072/4096 bit) for bitstream and user data protection
- Device Identifier Composition Engine (DICE), Security Protocol and Data Model (SPDM), and Lattice SupplyGuard capable, providing attestation and secure lifecycle/supply chain management for future-proof, end-to-end security
Hardware root of trust (RoT)
- Trusted single-chip boot with integrated flash
- Unique device secret (UDS) ensuring distinct device identity
- Integrated non-volatile configuration memory and user flash memory (UFM) with flexible partitioning and secure locking
- Comprehensive locking control of programming interface (SPI, JTAG), providing complete protection
- Side Channel Attack (SCA) resiliency and NIST Cryptographic Algorithm Validation Program (CAVP) compliant algorithms
Lattice also expanded its RoT-enabled Lattice MachXO5-NX device family with new MachXO5-NX TD devices that offer new density and package options. These new Lattice MachXO5-NX TDQ and MachXO5-NX TD FPGA devices are available and have shipped to Communications and Compute customers, and are supported by the latest release of Lattice Radiant design software.
